1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including advanced transistor elements that comprise strain-inducing semiconductor alloys.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity which in turn causes an increase of gate resistivity due to the reduced dimensions, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant role of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, during anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a strong dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 80 nm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although usage of high speed transistor elements having an extremely short channel may be restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with requirements for many types of circuits, even if only transistors in speed critical paths are formed on the basis of an extremely thin gate oxide.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer.
In addition to providing sophisticated gate electrode structures by using high-k dielectric materials and metal-containing gate electrode materials, other approaches have been developed in order to enhance transistor performance for a given gate length and a thickness of a gate dielectric material. For example, by creating a certain strain component in the channel region of the transistor elements, the charge-carrier mobility and thus the overall conductivity of the channel may be enhanced. For a silicon material having a standard crystallographic configuration, i.e., a (100) surface orientation with the channel length direction oriented along a <110> equivalent direction, the creation of a tensile strain component in the current flow direction may enhance conductivity of electrons, thereby improving transistor performance of N-channel transistors. On the other hand, generating a compressive strain component in the current flow direction may increase hole mobility and thus provide superior conductivity in P-channel transistors. Consequently, a plurality of strain-inducing mechanisms have been developed in the past which may per se require a complex manufacturing sequence for implementing the various strain-inducing techniques. For example, one promising approach that is frequently applied is the incorporation of a compressive strain-inducing silicon/germanium alloy in the drain and source areas of P-channel transistors. For this purpose, in an early manufacturing stage, cavities are formed selectively adjacent to the gate electrode structure of the P-channel transistor, while the N-channel transistors are covered by a spacer layer. Additionally, the gate electrode of the P-channel transistor has to be encapsulated in order to not unduly expose the gate electrode material to the etch ambient for forming the cavities and also for providing an efficient growth mask during the selective epitaxial growth process, in which the silicon/germanium alloy may be grown on a crystalline substrate material, while a significant deposition of the alloy on dielectric surface areas may be suppressed by appropriately selecting the corresponding process parameters.
A strain-inducing mechanism as described above is a very efficient concept for improving the transistor performance, at least for P-channel transistors, since, for a given gate length, an increased current drive capability may be achieved. The finally obtained strain component in the channel region significantly depends on the internal strain level of the silicon/germanium material, which in turn strongly depends on the lattice mismatch between the silicon/germanium alloy, i.e., its natural lattice constant, and the remaining template material of the silicon-based active region. Frequently, a desired increase of the germanium concentration in view of increasing the lattice mismatch may be associated with significant technological problems in view of germanium agglomeration and the creation of significant lattice irregularities so that germanium concentration levels of above 30 atomic percent are difficult to achieve on the basis of presently available selective epitaxial growth techniques. In addition to the germanium concentration, the effective offset of the strained silicon/germanium alloy from the channel region also strongly influences the finally achieved strain level in the channel region. Consequently, it is attempted to reduce the lateral offset of a corresponding cavity and thus of the resulting silicon/germanium alloy with respect to the channel region by reducing a width of spacer elements, which are typically used as a mask material during the above-described process sequence for forming the silicon/germanium alloy. Although reducing the lateral offset is considered an efficient mechanism for adjusting a desired high strain level, applying a spacer width of approximately 8 nm or less may result in significant yield losses, in particular when, additionally, sophisticated gate dielectric materials may be incorporated into the gate electrode structure. That is, frequently, the high-k dielectric material in combination with the work function adjusting metal species may be provided in an early manufacturing stage in order to enable the further processing on the basis of well-established electrode materials, such as silicon, silicon/germanium and the like. Consequently, the corresponding sidewall spacer may have to confine the sensitive materials and also the semiconductor electrode material, in particular during the selective epitaxial growth process. Upon reducing the width of the sidewall spacer element, irregularities of the upper edge of the gate electrode structures of the P-channel transistors have been observed, as will be explained in more detail with reference to FIGS. 1a and 1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 in combination with a silicon-based semiconductor layer 102. As is well known, the semiconductor layer 102 comprises a plurality of active regions, such as active regions 102A, 102B, which are to be understood as semiconductor regions in and above which transistor elements are to be formed, such as transistors 150A, 150B. It should be appreciated that the active regions 102A, 102B are laterally delineated by isolation structures (not shown), such as shallow trench isolations and the like. Moreover, in the vertical direction, the active regions 102A, 102B may be delineated by a buried insulating material (not shown), if a silicon-on-insulator (SOI) configuration is considered, while, in other cases, counter-doped areas may be formed around the respective active regions 102A, 102B in a crystalline material of the substrate 101, thereby implementing a “bulk” configuration. In the example shown, the transistor 150A may represent a P-channel transistor, which is to receive a compressive strain-inducing silicon/germanium alloy, as discussed above. On the other hand, the transistor 150B represents an N-channel transistor, which may not receive a strain-inducing semiconductor alloy and which has at least to be protected during the corresponding sequence for providing a silicon/germanium alloy in the transistor 150A.
In the manufacturing stage shown in FIG. 1a, the transistor 150A comprises a gate electrode structure 160A comprising a gate dielectric material 161, which may comprise a high-k dielectric material, such as hafnium oxide-based materials and the like. Furthermore, in this case, a conductive cap layer 162, which may also comprise a work function adjusting metal species, is formed above the material 161. Additionally, a silicon material, such as a polycrystalline silicon material 163, is provided above the layer 162 and may also be referred to as an electrode material, although it should be noted that the material 162 may also act as an electrode material. Furthermore, a dielectric cap layer 164, for instance a silicon nitride material, is provided on top of the silicon material 163. Furthermore, a spacer element 166S may be formed in combination with a silicon oxide liner 165, at least on a portion of the sidewalls of the gate electrode structure 160A. As previously discussed, at least the spacer element 166S is to confine the sensitive materials 161, 162 and also has to protect integrity of the material 163, which in turn is protected by the oxidized portion 165. A gate electrode structure 160B of the transistor 150B comprises the materials 161 and 162, which may have a different composition compared to the material 162 of the gate electrode structure 160A, for instance, with respect to a work function adjusting species and the like. Moreover, the material 163 may have formed thereon the oxidized portion 165, while a spacer layer 166 may cover the gate electrode structure 160B and the active region 102B. Moreover, an oxide layer 165, which may be formed together with the oxide liner 165 and the materials 163, may be positioned between the active region 102B and the spacer layer 166.
As previously discussed, a thickness of the spacer layer 166 is desirably selected as thin as possible so as to obtain the spacer elements 166S in the transistor 150A with a minimum width in order to reduce an offset of cavities 151 to be formed in the active region 102A. On the other hand, a sufficient degree of material confinement has to be ensured by the spacer element 166S, which may, however, be increasingly compromised upon further reducing the thickness of the spacer layer 166 and thus of the width of the spacers 166S.
Typically, the semiconductor device 100 as illustrated in FIG. 1a is formed on the basis of the following processes. After providing corresponding isolation structures (not shown), the basic dopant concentration in the active regions 102A, 102B is established. Thereafter, appropriate materials for the gate dielectric material 161 and the cap layers 162 may be provided, possibly in combination with a corresponding patterning regime, so as to provide different metal-containing material systems for the transistors 150A, 150B in order to adjust the appropriate work function for the transistors 150A, 150B. It should be noted that, if required, an additional threshold adjusting semiconductor material may be provided in one of the active regions 102A, 102B, for instance on the basis of epitaxial growth techniques in order to enable a desired adjustment of the work function for available metal species that are typically used for adjusting the work function of P-channel transistors and N-channel transistors, respectively. For example, a silicon/germanium alloy may be selectively formed on the active region 102A prior to forming the gate electrode structures 160A, 160B. Thereafter, the silicon material 163 may be deposited in combination with a dielectric cap layer 164 and with additional materials, such as anti-reflective coating (ARC) materials, hard mask materials and the like, as are required for performing sophisticated lithography and etch processes to obtain the gate electrode structures 160A, 160B with critical dimensions of 50 nm and less. After the patterning sequence, the spacer layer 166 is deposited, preceded by an oxidation process for forming the oxide liners 165. For example, a typical oxide thickness may be in the range of 2 nm, while the spacer layer 166 may be deposited with a thickness of approximately 10 nm. It should be appreciated that, if required, a silicon nitride liner material may be deposited, for instance, as a part of the spacer layer 166 if an enhanced density material may be required which may be accomplished on the basis of thermally activated chemical vapor deposition (CVD) techniques and the like. Next, a resist mask 103 is provided to cover the transistor 150B while exposing the transistor 150A to an etch ambient 104 in which the spacer layer 166 may be etched so as to obtain the spacer element 166S. Since a plasma assisted silicon nitride etch process may have a lateral etch component, the initial thickness of the spacer layer 166 may be reduced, thereby resulting in spacer elements having a width of approximately 8 nm or less, which would be desirable in view of reducing the offset of the cavities 151 with respect to a channel region 152. Thereafter, the etch chemistry may be changed so as to etch into the silicon material of the active region 102A, while using the spacer element 166S and the cap layer 164 as an etch stop material. It should be appreciated that this etch phase may also include an etch step for removing oxide materials, which may still be formed on the active region 102A due to the preceding oxidation process. Consequently, upon selecting a reduced initial width of the spacer layer 166, there is a certain risk of exposing the oxide liner 165 at a top corner 160T (FIG. 1b), which may thus be attacked during the corresponding etch step.
After forming the cavities 151, the resist mask 103, if still provided, may be removed and appropriate cleaning processes are performed, for instance, based on diluted hydrofluoric acid (HF), which is known to efficiently remove contaminants, etch byproducts and silicon oxide materials. Thus, any exposed areas of the oxide liner 165 may be further attacked so that even the material 163 may be locally exposed during the corresponding process sequence. Furthermore, prior to the actual selective epitaxial growth process, a further cleaning process may be performed, which may also result in an additional exposure of material 163 at the top corner 160T.
FIG. 1b schematically illustrates the semiconductor device 100 when exposed to a selective epitaxial growth process 105, in which a silicon/germanium material 153 is grown in the cavities 151 (FIG. 1a), while the spacer layer 166 acts as a growth mask for the transistor 150B. On the other hand, the spacer 166S in combination with the cap layer 164 have to provide integrity of the electrode material 163 whose integrity, however, may have been compromised during the preceding process, in particular at the top area 160T, as discussed above. Thus, during the selective epitaxial growth process 105, silicon/germanium material residues 153R may form at the top corner 160T, wherein the size of these residues 153R may depend on the degree of exposure of the material 163, which in turn strongly depends on the initial thickness of the layer 166 and thus of the width of the spacers 166S.
During the further processing, respective spacers 166S may also be formed on the gate electrode structure 160B while masking the transistor 150A, and the spacers 166S may be used, possibly in combination with additional spacer elements, as an implantation mask for forming drain and source extension regions by ion implantation. In other cases, the spacer layer 166, the spacers 166S and the dielectric cap material 164 may be removed and the further processing may be continued by forming appropriate offset spacer elements for the subsequent incorporation of dopant species for providing the drain and source extension regions. In any case, the material residues 153R may significantly influence the subsequent processing, for instance resulting in an increased shadowing effect for subsequent implantation processes or spacer forming processes and the like. Furthermore, at a very advanced manufacturing stage, metal silicide regions may have to be formed in the active regions 102A, 102B and also in the material 163 of the gate electrode structures 160A, 160B, wherein the residues 153R may further negatively affect the silicidation process and may thus result in significant modifications of the overall transistor characteristics.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.